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INTEGRATED CIRCUITS
PCKV857 70-190 MHz differential 1:10 clock driver
Product data Supersedes data of 2001 Mar 16 File under Intergrated Circuits ICL03 2001 Jun 12
Philips Semiconductors
Philips Semiconductors
Product data
70-190 MHz differential 1:10 clock driver
PCKV857
FEATURES
* ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114.
PIN CONFIGURATION
GND 1 Y0 2 Y0 3 VDDQ 4 Y1 5 Y1 6 GND 7 GND 8 Y2 9 Y2 10 VDDQ 11 VDDQ 12 CLK 13 CLK 14 VDDQ 15 AVDD 16 AGND 17 GND 18 Y3 19 Y3 20 VDDQ 21 Y4 22 Y4 23 GND 24 48 GND 47 Y5 46 Y5 45 VDDQ 44 Y6 43 Y6 42 GND 41 GND 40 Y7 39 Y7 38 VDDQ 37 PWRDWN 36 FBIN 35 FBIN 34 VDDQ 33 FBOUT 32 FBOUT 31 GND 30 Y8 29 Y8 28 VDDQ 27 Y9 26 Y9 25 GND
* Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA
* Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications as per JEDEC specifications
* 1-to-10 differential clock distribution * Very low skew (< 100 ps) and jitter (< 100 ps) * Operation from 2.2 V to 2.7 V AVDD and 2.3 V to 2.7 V VDD * SSTL_2 interface clock inputs and outputs * CMOS control signal input * Test mode enables buffers while disabling PLL * Low current power-down mode * Tolerant of Spread Spectrum input clock * Full DDR solution provided when used with SSTL16877 or
SSTV16857
* See PCKV856 for I2C capable clock driver
DESCRIPTION
The PCKV857 is a high-performance, low-skew, low-jitter zero delay buffer designed for 2.5 V VDD and 2.5 V AVDD operation and differential data input and output levels. The PCKV857 is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock outputs (FBOUT, FBOUT) . The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog power input (AVDD). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to high impedance state (3-State), and the PLL is shut down (low power mode). The device also enters the low power mode when the input frequency falls below 20 MHz. An input frequency detection circuit will detect the low frequency condition and after applying a > 20 MHz input signal, the detection circuit turns on the PLL again and enables the outputs. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The PCKV857 is also able to track spread spectrum clocking for reduced EMI. The PCKV857 is characterized for operation from 0 to +70 C.
SW00691
ORDERING INFORMATION
PACKAGES 48-Pin Plastic TSSOP TEMPERATURE RANGE 0 to +70 C ORDER CODE PCKV857DGG DRAWING NUMBER SOT362-1
2001 Jun 12
2
853-2242 26485
Philips Semiconductors
Product data
70-190 MHz differential 1:10 clock driver
PCKV857
PIN DESCRIPTION
PINS 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 2, 3, 5, 6, 9, 10, 19, 20, 22, 23, 26, 27, 29, 30, 32, 33, 39, 40, 43, 44, 46, 47 4, 11, 12, 15, 21, 28, 34, 38, 46 13, 14, 35, 36 16 17 37 SYMBOL GND Yn, Yn, FBOUT, FBOUT VDDQ CLKIN, CLKIN, FBIN, FBIN AVDD AGND PWRDWN DESCRIPTION SSTL_2 ground pins SSTL_2 differential outputs SSTL_2 power pins SSTL_2 differential inputs Analog power Analog ground Power-down control input
FUNCTION TABLE
INPUTS PWRDWN L L H H X2 CLK L H L H < 20 MHz CLK H L H L < 20 MHz Yn Z Z L H Z Yn Z Z H L Z OUTPUTS FBOUT Z1 Z1 L H Z1 FBOUT Z1 Z1 H L Z1 PLL ON/OFF OFF OFF ON ON OFF
NOTES: H = HIGH voltage level L = LOW voltage level Z = high impedance OFF-state X = don't care 1. Subject to change. May cause conflict with FBIN pins. 2. Additional feature that senses when the clock input is less than 20 MHz and places the part in sleep mode.
BLOCK DIAGRAM
37 - PWRDWN 3 - Y0 2 - Y0 5 - Y1 6 - Y1 10 - Y2 9 - Y2 20 - Y3 19 - Y3 22 - Y4 13 - CLK 14 - CLK PLL 36 - FBIN 35 - FBIN 16 - AVDD 23 - Y4 46 - Y5 47 - Y5 44 - Y6 43 - Y6 39 - Y7 40 - Y7 29 - Y8 30 - Y8 27 - Y9 28 - Y9 32 - FBOUT 33 - FBOUT
SW00692
2001 Jun 12
3
Philips Semiconductors
Product data
70-190 MHz differential 1:10 clock driver
PCKV857
ABSOLUTE MAXIMUM RATINGS1
SYMBOL VDDQ AVDD VI VO IIK IOK IO Tstg PARAMETER Supply voltage range Supply voltage range Input voltage range Output voltage range Input clamp current Output clamp current Continuous output current Continuous current to GND or VDDQ Storage temperature range see Notes 2 and 3 see Notes 2 and 3 VI < 0 or VI >VDDQ VO < 0 or VO >VDDQ VO = 0 to VDDQ CONDITION LIMITS MIN 0.5 0.5 -0.5 -0.5 -- -- -- -- -65 MAX 3.6 3.6 VDDQ + 0.5 VDDQ + 0.5 50 50 50 100 +150 UNIT V V V V mA mA mA mA C
NOTES: 1. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This value is limited to 3.6 V maximum.
RECOMMENDED OPERATING CONDITIONS1
SYMBOL VDDQ AVDD VIL PARAMETER Supply voltage range Supply voltage range g Low level input voltage CLK, CLK, FBIN, FBIN PWRDWN VIH g g High level input voltage DC input signal voltage VID VOX VIX IOH IOL SR Tamb DC differential input signal voltage AC differential input signal voltage Output differential cross-voltage Input differential cross-voltage High-level output current Low-level output current Input slew rate Operating free-air temperature CLK, FBIN CLK, FBIN CLK, CLK, FBIN, FBIN PWRDWN Note 2 Note 3 Note 3 Note 4 Note 4 CONDITION LIMITS MIN 2.3 2.2 -- -0.3 VDDQ/2 + 0.18 1.7 -0.3 0.36 0.7 VDDQ/2 - 0.2 VDDQ/2 - 0.2 -- -- 1 0 TYP -- -- -- -- -- -- -- -- -- VDDQ/2 -- -- -- -- -- MAX 2.7 2.7 VDDQ/2 - 0.18 0.7 -- VDDQ + 0.3 VDDQ VDDQ + 0.6 VDDQ + 0.6 VDDQ/2 + 0.2 VDDQ/2 + 0.2 -12 12 4 70 V V V V V mA mA V/ns C V UNIT V V V
NOTES: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential input signal voltage specifies the differential voltage |VTR - VCP| required for switching, where VTR is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be crossing.
2001 Jun 12
4
Philips Semiconductors
Product data
70-190 MHz differential 1:10 clock driver
PCKV857
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL VIK VO OH PARAMETER Input voltage, all inputs High-level High level output voltage TEST CONDITIONS VDDQ = 2.3 V, II = -18 mA VDDQ = min to max, IOH = -1 mA VDDQ = 2.3 V, IOH = -12 mA VDDQ = min to max, IOL = 1 mA VDDQ = 2.3 V, IOL = 12 mA VDDQ = 2.7 V, VI = 0 V to 2.7 V VDDQ = 2.7 V, VO = VDDQ or GND CLK and CLK = 0 MHz, PWRDWN = low; of IDD and AIDD fO = 67 MHz to 190 MHz fO = 67 MHz to 190 MHz VCC = 2.5 V, VI = VCC or GND MIN -- VDDQ - 0.1 1.7 -- -- -- -- -- -- -- 2 TYP -- -- -- -- -- -- -- 30 200 8 2.8 MAX -1.2 -- -- 0.1 0.6 10 10 100 300 10 3 UNIT V V V V V A A A mA mA pF
VO OL II IOZ IDDPD IDD AIDD CI
Low-level Low level output voltage Input current High-impedance-state output current Power-down current on VDDQ + AVDD Dynamic current on VDDQ Supply current on AVDD Input capacitance
NOTE: 1. This is intended to operate in the SSTL_2 type IV unterminated mode without series resistors on the outputs. 2. All typical values are at respective nominal VDDQ. 3. Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing.
TIMING REQUIREMENTS
Over recommended ranges of supply voltage and operating free-air temperature. SYMBOL fCK Operating clock frequency Input clock duty cycle Stabilization time1 PARAMETER MIN 60 40 100 MAX 190 60 -- UNIT MHz % s
NOTE: 1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power-up.
2001 Jun 12
5
Philips Semiconductors
Product data
70-190 MHz differential 1:10 clock driver
PCKV857
AC CHARACTERISTICS
SYMBOL t(O) tSK(O) tSLR(O) tJIT(PER) tJIT(CC) tJIT(HPER) tPLH1 tPHL1
GND = 0 V; tr = tf 2.5 ns; CL = 50 pF; RL = 1 k LIMITS PARAMETER Static phase offset Output clock skew Output clock skew rate Jitter (period) Jitter (cycle-to-cycle) Half-period jitter Low to high level propagation delay High to low level propagation delay WAVEFORM Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Test mode/CLK to any output Test mode/CLK to any output fO = 67 MHz to 200 MHz fO = 67 MHz to 200 MHz CONDITION MIN -150 -- 1 -75 -75 -100 -- -- TYP 0 -- -- -- -- -- 3.7 3.7 MAX 150 75 2 75 75 100 -- -- UNIT ps ps V/ns ps ps ps ns ns
NOTE: 1. Refers to transition of noninverting output.
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
FRONT SIDE SSTL16877 or SSTV16857 PCKV857 SSTL16877 or SSTV16857
The PLL clock distribution device and SSTL registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation
SDRAM
SW00688
2001 Jun 12
6
Philips Semiconductors
Product data
70-190 MHz differential 1:10 clock driver
PCKV857
AC WAVEFORMS
CLK CLK
FBIN FBIN t(O)n t(O)n + 1 n =N 1 N t(O)n (N is a large number of samples)
t(O) =
SW00882
Figure 1. Static phase offset
Yx Yx
Yx, FBOUT Yx, FBOUT tsk(O)
SW00883
Figure 2. Output skew
80%
80% VID, VOD
20% CLOCK INPUTS AND OUTPUTS tSLR(I), tSLR(O) tSLR(I), tSLR(O)
20%
SW00886
Figure 3. Input and output slew rates
2001 Jun 12
7
Philips Semiconductors
Product data
70-190 MHz differential 1:10 clock driver
PCKV857
Yx, FBOUT Yx, FBOUT tcycle n
Yx, FBOUT Yx, FBOUT
1
fO tJIT(PER) = tcycle n - 1 fO
SW00884
Figure 4. Period jitter
tcycle n Yx, FBOUT Yx, FBOUT
tcycle n + 1
tJIT(CC) = tcycle n - t cycle n+1
SW00881
Figure 5. Cycle-to-cycle jitter
Yx, FBOUT Yx, FBOUT thalf period n thalf period n + 1
1
fO tJIT(HPER) = thalf period n - 1 2*fO
SW00885
Figure 6. Half-period jitter
skew
ANY TWO OUTPUTS
SW00396
Figure 7. Skew between any two outputs.
2001 Jun 12
8
Philips Semiconductors
Product data
70-190 MHz differential 1:10 clock driver
PCKV857
t1
t2
45% v
t1 v 55% t1 ) t2
SW00397
Figure 8. Duty cycle limits and measurement
TEST CIRCUIT
VDD/2
PCKV857
C = 14 pf Z = 60 -VDD/2 R = 10 Z = 50
SCOPE
R = 50
Z = 60
R = 10
Z = 50
VTT
C = 14 pf -VDD/2
R = 50
VTT -VDD/2 NOTE: VTT = GND
SW00880
Figure 9. Output load test circuit
2001 Jun 12
9
Philips Semiconductors
Product data
70-190 MHz differential 1:10 clock driver
PCKV857
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
2001 Jun 12
10
Philips Semiconductors
Product data
70-190 MHz differential 1:10 clock driver
PCKV857
NOTES
2001 Jun 12
11
Philips Semiconductors
Product data
70-190 MHz differential 1:10 clock driver
PCKV857
Data sheet status
Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. Date of release: 06-01 Document order number: 9397 750 08475
Philips Semiconductors
2001 Jun 12 12

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